India launches DHRUV64, first indigenously designed 1.0 GHz 64-bit microprocessor

India has unveiled DHRUV64, a homegrown 1.0 GHz, 64-bit dual-core microprocessor designed by the Centre for Development of Advanced Computing under the Microprocessor Development Programme, a milestone that government officials say strengthens the domestic chip design ecosystem and reduces long-term import dependence. The launch took place on 16 December 2025, according to an official release and multiple media reports.

What DHRUV64 brings to the table

DHRUV64, also referenced as VEGA AS2161, is based on the open RISC‑V 64G instruction set and features a dual-core, out‑of‑order engine with a 13 to 16 stage pipeline, floating‑point support, MMU for Linux, configurable L1 and L2 caches, and a high‑performance interconnect.

It targets strategic and commercial use cases across 5G infrastructure, automotive, industrial and consumer systems, as per C-DAC’s technical notes and coverage by embedded systems trackers. The chip boots Linux and has working or in‑progress ports for Zephyr and FreeRTOS, providing developers with familiar toolchains and real‑time options.

Part of India’s RISC‑V push

DHRUV64 is the third design publicised under the Digital India RISC‑V, or DIR‑V, programme after THEJAS32 and THEJAS64. Earlier indigenous efforts such as SHAKTI from IIT Madras and AJIT from IIT Bombay laid the groundwork for an Indian processor ecosystem. Officials add that work has begun on next‑generation Dhanush and Dhanush+ variants.

While the design is indigenous, public material has not specified the foundry used for DHRUV64 fabrication. Analysts tracking prior DIR‑V tape‑outs note that THEJAS64 was fabricated at SCL Mohali on a 180 nm process and infer that DHRUV64 may be made offshore until more advanced domestic capacity is available.

DIR‑V follows earlier Indian processor projects like SHAKTI and AJIT, and recent DIR‑V tape‑outs THEJAS32 and THEJAS64 with the latter fabricated at SCL Mohali, a trajectory that officials say is building design confidence and domestic capability.

Leadership driving India’s semiconductor push

C-DAC Director General E Magesh has been steering national programmes across supercomputing and microprocessors, with DIR‑V positioned by MeitY as a pathway to Aatmanirbhar Bharat in semiconductors. Industry watchers say DHRUV64 signals a maturing of India’s chip design talent into production‑grade silicon.

How will developers get started on DHRUV64?

According to C-DAC literature, the VEGA family exposes a standard RISC‑V toolchain environment with JTAG debug, Eclipse and GDB support, plus AXI‑compliant interfaces for broader system integration. This alignment with open tooling, developers said, should shorten bring‑up cycles for boards and reference designs built around DHRUV64.

Why this matters

Analysts point out that a domestically designed, Linux‑capable, dual‑core 64‑bit processor helps India seed secure compute in defence, communications and industrial systems while expanding homegrown IP. It also gives startups and academia a supported platform to prototype without relying entirely on imported cores. Government communications underline its role in skilling and ecosystem development.

The road ahead

As per programme updates, C-DAC and partners are moving toward Dhanush and Dhanush+ SoC variants. Observers expect higher clocks, broader I/O and tighter integration if the roadmap stays on track, though details will depend on process nodes and manufacturing partnerships.